1. Field of the Invention
The present invention relates to a synchronous memory device of a wave pipeline structure. More particularly, it relates to a synchronous memory device of a wave pipeline structure which improves data access time by reducing the data access path, thus enhances the stability and performance of a memory operation and achieves a high-speed operation.
2. Description of the Prior Art
Conventionally, various kinds of pipeline structures have been applied to a synchronous memory device in order to achieve a high-speed column path. A wave pipeline structure which is one of the pipeline structures and uses a plurality of registers at its output terminal, has a relatively simple circuit embodied on a small area and also has advantage to a high-speed operation.
FIG. 1A is a block diagram of a conventional synchronous memory device of a wave pipeline structure, and it schematically shows a column path during a read operation.
Referring to FIG. 1A, if a read command is input, a column address signal passing through a column address buffer 1 is synchronized by an internal clock signal ICLK, is set to a burst column address counter 3, passes through a column address decoder 5, and thus accesses a bit line sense-amp inside of a bank 7 corresponding to a column address.
At this time, a column selection signal Yi generated from the column address decoder 5 transmits the data being sensed and amplified by the bit line sense-amp to local input/output lines L.sub.-- IO and /L.sub.-- IO. The transmitted data is amplified by an input/output sense-amp (IO S/A) 9, passes through a global input/output line G.sub.-- IO, and is stored in one register among N registers 11-1n (register0 registerN-1).
In addition, there is a read data controller 20 in an output terminal, the read data controller 20 generates an output enable signal OE for controlling an output driver 30, an input control signal PI&lt;0:N-1&gt; of the N registers 11-1n, and an output control signal PO&lt;0:N-1&gt; of the N registers 11-1n, thereby controlling output data.
Thereafter, whenever data is transmitted after passing through global input/output line G.sub.-- IO by a burst read operation, the input control signals PI&lt;0:N-1&gt; of the registers are sequentially activated, the inputs of the registers are sequentially controlled, and thus the data are sequentially stored in the registers 11-1n. Since the register output control signals PO&lt;0:N-1&gt; are sequentially activated from `CL-1`-th clock after a read command, the data stored in the registers 11-1n are sequentially outputted to a data output pin DQ-pin via the output driver 300.
Generally, a burst length BL is greater than the number N of registers in a burst read operation. But, there is no problem in a data output operation even if the data is input again to a register having stored data, because the stored data is already outputted.
FIG. 1B is an operation timing diagram of the synchronous memory device shown in FIG. 1A. FIG. 1B illustrates a relation among an internal clock signal ICLK, the register data output control signals PO&lt;0:N-1&gt; and a data output DQ, in case that a CAS (column address strobe) latency CL is set to 3 and a burst length BL is set to 4.
As shown in FIG. 1B, a data output control signal PO&lt;0&gt; of a first register (register0) is activated by `CL-1`-th clock from a read command input clock, and then the data stored in the register (registers) is outputted to the data output pin DQ-pin via the output driver 30. According to this method, the output control signals PO&lt;1&gt;, PO&lt;2&gt; and PO&lt;0&gt; are sequentially activated by the next clock signal, so that the data stored into a plurality of registers (register1, register2 and register0) are sequentially outputted to the data output pin DQ-pin.
Although register input control signal PI&lt;0:2&gt; is not shown in FIG. 1B, the input control signals PI&lt;O&gt;, PI&lt;1&gt;, and PI&lt;2&gt; are activated whenever the data is transmitted to the output terminal via the global input/output line, so that a plurality of transmission gates MTI.sub.-- 0, MTI.sub.-- 1 and MTI.sub.-- 2 connected to the input terminals of the registers are turned on. Therefore, the data are sequentially stored into the registers.
By this operation method, a data access time tAC in the conventional synchronous memory device is determined by the sum of a skew from an external clock to an internal clock, a delay from the internal clock to a register output control signal PO, and a delay from a register controlled by the register output control signal PO to a data output pin.
Also, the conventional synchronous memory device having a wave pipeline structure controls output data by sequentially controlling an input/output operation of N registers positioned at each output terminal. At this time, the register output control signals PO&lt;0:N-1&gt; are generated by using a rising edge of the clock as a standard, and they control each output of the registers.
However, in this case, since several logic gates are needed between the external input clock CLK and the register output control signals, a high-speed operation of the data is limited, and a clock skew between the external clock signal CLK and the internal clock signal ICLK occurs. As a result, if a large-sized chip is used, the high-speed operation becomes more difficult.